The inventive concepts described herein generally relate to semiconductor devices, and more particularly, to delay-locked loop (DLL) circuits which may be used, for example, in synchronous memory devices.
In certain types of semiconductor memory devices, such as Rambus DRAM (RDRAM) devices and synchronous DRAM (SDRAM) devices, a DLL circuit may operate in synchronization with reference clock signals, that is, external clock signals. The DLL circuit receives the external clock signals and generates internal clock signals which are delayed for a predetermined time period, where the internal clock signals are used as clock signals by components of a semiconductor memory device.
A DLL circuit is generally worst-case designed so that it is operational at the highest possible operating frequency of the semiconductor memory device. This can result in current consumption inefficiencies at lower operating speeds, as well as deterioration of duty cycle correction characteristics at lower operation speeds.